The present invention generally relates to an arrangement that generates periodic electrical signals, and more particularly, to a signal generator for a microprocessor, and to a method.
Many applications, such as microprocessors, require a clock having a high frequency. While quartz oscillators operate at a lower frequency, conversion is often required.
FIG. 1 illustrates a simplified block diagram of a phase-locked loop (PLL) circuit. The PLL circuit has a phase comparator (PC), a low pass filter (LPF) with capacitor, and a voltage controlled oscillator (VCO). The PLL circuit provides that the frequency FOUT of the output signal Y remains locked to the frequency FREF of the input signal X (or to a multiple of FREF). The phase comparator detects phase differences between the input signal X and the output signal Y and acts on the VCO to minimize the difference.
It is desired to integrate the complete PLL circuit and the processor into a monolithic integrated chip. For many xe2x80x9con-chipxe2x80x9d applications, the input signal X has a low reference frequency (e.g., FREF≈32 kHz) and the output signal Y has a very high output frequency (e.g., FOUT≈100 . . . 200 MHz). Frequency multiplication is required by a factor FOUT/FREF of about 3000 . . . 6000. Since noise influence increases frequency variations, the PLL circuit would require a large capacitor (e.g., 10 nF) external to the chip and connected by an unwanted extra pin. Integrating the capacitor would be difficult too; for example, the silicon area of such a capacitor would be larger than the area of the PLL circuit itself.
There in an ongoing need to provide an improved PLL circuit as well as a method that mitigate some or all of these and other disadvantages and limitations of the prior art.